1. Technical Field
The present application relates generally to semiconductor devices, include semiconductor devices used in high voltage applications.
2. Related Art
Laterally diffused metal oxide semiconductor (LDMOS) devices are typically used in high voltage applications. FIG. 1 shows an example of a conventional LDMOS. The LDMOS in FIG. 1 includes a high-voltage N-well (HVNW) region 102 on a P-type substrate 100. A P-type well 110 and a N-type well 120 are formed in the HVNW region 102. A gate is formed by a gate oxide layer 175 and a polysilicon gate layer 170. Also, a portion of the gate layer 170, referred to as the field plate, extends over a central field oxide (FOX) region 162. The relatively thick central FOX region 162 serves to increase the breakdown voltage of the device by reducing electric field crowding at the gate edge. Further, two additional FOX regions 160 and 164 are formed, one at each side of the LDMOS device, which serve to isolate the device from other devices. An N+ doped region 180 is formed within the N-type well 120 in order to form a drain region, and another N+ doped region 185 is formed in the P-type well 110 in order to form a source region. In addition, with regard to the N+ doped region 185 formed in the P-type well 110, an adjacent P+pickup region 190 is provided to reduce resistivity. The LDMOS device shown in FIG. 1 can be manufactured as disclosed by U.S. Pat. No. 7,192,834, which is hereby incorporated by reference.
When designing LDMOS devices, it is desirable for the device to have a very high breakdown voltage (Vbd), while also exhibiting a low on-resistance (Ron) during operation. LDMOS devices having a low on-resistance and a high breakdown voltage will typically exhibit a relatively lower power loss when used for high-voltage applications. One problem when designing such LDMOS devices is that techniques and structures that tend to maximize the breakdown voltage Vbd tend to adversely affect the on-resistance Ron, and vice versa.
Thus, it is desirable to find new approaches for improving trade-off between the breakdown voltage and on-resistance of LDMOS devices, particularly so as to allow for shrinking the feature size of LDMOS devices without degrading the device characteristics.